The advent of wireless and mobile technologies increases the demand for low power integrated circuit designs, particularly for use in battery-powered applications. Because the architectural choices for an integrated circuit (or chip) design often determines its power characteristics, it is becoming imperative to assess the power dissipation level of a chip design at an early stage in the design cycle where significant design changes can still be made to optimize the power characteristics.
In a typical design process of an integrated circuit, the chip design, defined by a functional specification and an interface description, is created using a computer aided design tool and expressed at the register-transfer level (RTL) using a hardware description language (HDL), such as Verilog. HDL describes the chip design in behavior terms and does not include a detailed structural description of the design. When the designer is satisfied with the design at the register-transfer level, the RTL chip design is then synthesized to transform the behavior description into a circuit level or a gate level description. The circuit level or gate level description may be further optimized and verified before the design is transformed into a mask set for manufacturing the integrated circuit.
Generally, a power model of a cell (or a gate) contains one or more descriptions of power dissipating conditions associated with the cell. Two types of cell power models have found widespread use: pin-based and arc-based. Pin-based models describe power dissipation of a cell based on single transitions (switches) on one of the cell's pins, possibly under specific Boolean conditions describing the states of the other pins. The evaluation of the power model involves using the activity values (that is, the switching activity or the duty cycle) of each pin. Arc-based power models describe power dissipation of a cell based on a sequence of events (or logical transitions) on the cell's pins. The sequence of events is usually a transition on an input pin followed by a transition on an output pin, called an arc. Hence, the power model is “arc” based. More complicated arc-based power models may reference a sequence of more than two transitions, or include a Boolean condition describing logical states on the cell's pins during this sequence. The conventional power model uses arc-based power modeling with two kinds of power arcs: the transaction power arc and the intrinsic power arc. With these two kinds of power arcs, the silicon power consumption may be modeled very accurately based on the simulation transaction.
The Liberty library format developed by Synopsys, Inc. is a pin-based modeling technique. However, for the Liberty library format, work has not been done for accurately defining how to characterize (model) memory power for estimation tools. Furthermore, memory power is difficult to model using pin-based characterization. The memory power model is more complex than the macro cells power model due to the structure of multiple input pins and multiple output pins, and because at any time many (any) types of input pins (CLK, Address, Data IN, write enable, etc.) can be active and they all may have some contribution to the overall power dissipation. The conventional memory power model is too simple to correlate with silicon power consumption.
Thus, it is desirable to provide a method and system that characterize and specify the power for each pin in a memory in such a way that they do not overlap with one another so that they can be combined to estimate the power accurately, which method may avoid redundancy caused by simultaneous switching of multiple pins.